This invention relates to a method of improving the electrical conductivity of transparent conducting lines carried on a substrate. In particular the invention is concerned with increasing the conductivity of addressing lines comprising transparent conducting material in pixellated devices such as active matrix liquid crystal displays. The invention also relates to the transistor substrate, known as the active plate, used in the manufacture of such displays.
An active matrix liquid crystal display (AMLCD) typically comprises an active plate and a passive plate between which liquid crystal material is sandwiched. The active plate comprises an array of transistor switching devices, typically with one transistor associated with each pixel of the display. Each pixel also has a pixel electrode on the active plate to which a signal is applied for controlling the display output of the individual pixel. Liquid crystal displays may be arranged as transmissive or reflective devices.
FIG. 1 shows the electrical components which make up the pixels of one known example of active plate of an AMLCD. The pixels are arranged in rows and columns. The row address conductor 10 of a pixel is connected to the gate of the TFT 12, and the column address conductor 14 is coupled to the source. The liquid crystal material provided over a pixel electrode of the pixel effectively defines a liquid crystal cell 16 which is connected between the drain of the transistor 12 and a common ground plane 18. An optional pixel storage capacitor 20 is connected between the drain of the transistor 12 and the row conductor 10 associated with an adjacent row of pixels.
For transmissive displays, a large area of the active plate is at least partially transparent, and this is required because the display is typically illuminated by a back light. In conventional display devices, the pixel electrode must be transparent, whereas row and column conductors are formed as metallic opaque lines. Metallic layers, such as chromium, molybdenum, aluminium, alloys or multilayer structures, are used for the row and column conductors because of the high conductivity, which improves the device performance. The conductivity of the lines (usually the column lines) to which the pixel drive signals are applied is particularly important in large displays, because a sizeable voltage drop occurs over the length of the line, making it impossible to drive uniformly all pixels along the line (column).
A problem with the use of metallic column conductors is that separate deposition and lithographic procedures are required to form the column conductors and the pixel electrodes. The pixel electrodes must be transparent, and are typically formed from a transparent conductive oxide film. It is well known that the lithography steps in the manufacturing process are a major contributing factor to the expense of the manufacturing process. Each lithographic step can be considered to reduce the yield of the process, as well as increasing the cost.
A conventional manufacturing process for the active plate of an LCD is a five mask process. With reference to the bottom gate TFT LCD active plate shown in FIG. 2, the process steps, each requiring a separate mask definition, are:
(i) defining the gate 22 (which is part of the row conductor) over the substrate 21;
(ii) defining the amorphous silicon island (which overlies a gate dielectric 23 that covers the entire structure), comprising a lower intrinsic layer 24 and an upper doped contact layer 26;
(iii) defining the metallic source 28, drain 30 and column electrode 32;
(iv) defining a contact hole 34 in a passivation layer 36 which covers the entire substrate; and
(v) defining the transparent pixel electrode 38 which contacts the drain 30 through the hole 34.
The capacitor shown in FIG. 1 may simply be formed from the gate dielectric by providing an area of overlap of one pixel electrode with a portion of the row/gate conductor of the adjacent row.
There have been various proposals to reduce the number of lithography steps, and thereby the mask count, of the manufacture process in order to reduce cost and increase yield.
For example, it has been proposed to form the column conductors from the same transparent conductive oxide film as the pixel electrode, so that these components of the pixel structure can be deposited and patterned together. Additional measures can result in a two mask process, and this is explained with reference to the bottom gate TFT LCD active plate shown in FIG. 3. The process steps, each requiring a separate mask definition, are:
(i) defining the gate 22 (and row conductors); and
(ii) defining the transparent column conductor 32 (which also forms the TFT source 28) and the pixel electrode 38 (which also forms the TFT drain 30).
The definition of the semiconductor island 24, 26 can be achieved by a self-aligned process using the gate 22, for example by using light exposure through the substrate. Of course, the semiconductor could equally be formed with a third mask step (between steps (i) and (ii) above). In the periphery of the array, the gate dielectric 23 is etched away using a low-precision stage, to allow contact to the gate lines at the periphery of the display.
In this structure, the high resistivity of the transparent conductive oxide thin film used for the column lines prevents the use of the structure in large (TV-sized) displays or in higher resolution displays, for example above VGA.
For this reason, there are further proposals to treat the column conductor area of the layer to increase the conductivity, whilst not affecting the transparency of the pixel electrode. One possibility would be to electroplate the top of the conducting lines with a metal but this technique has been found to have problems as, due to the resistive nature of the lines being plated, wide variations in the plating thickness over the length of the line tend to occur. Such thickness variations translate to variations in the LC cell gap which is highly undesirable. The article xe2x80x9cConductivity Enhancement of Transparent Electrode by Side-Wall Copper Electroplatingxe2x80x9d, J. Liu et al, SID 93 Digest, page 554 discloses a method of enhancing the conductivity by electroplating a copper bus to the side of the metal oxide column line. The process involves an incomplete etching process to leave metal oxide residues, which act as seeds for the copper growth. The process is, though, both complicated and difficult to control. In addition, the copper bus will surround the source and drain electrodes, and there is a risk of shorts between the source and drain resulting from fast lateral copper growth when forming the bus. The copper bus around the source and drain electrodes also influences the channel length of the TFT and therefore makes the TFT characteristics unpredictable.
WO 99/59024 discloses a method for enhancing the conductivity of a transparent electrode by providing patterned metallic layers adjacent to the transparent electrodes.
There is still a need for a simple and reliable process for increasing the conductivity of thin film lines of transparent metal oxide layer, such as ITO, without increasing dramatically the complexity of the process. Such a process will find application in active matrix LCD manufacture, but will also be useful for other technologies where mask count reduction could be achieved if a transparent conductive layer could be made to be more conductive at least in certain regions without losing the transparency in others. This may be of benefit for polymer LEDs and large area image sensors.
According to a first aspect of the invention, there is provided a method of improving the electrical conductivity of lines comprising transparent conducting material carried on a substrate, comprising the step of forming the lines of transparent conducting material on the substrate and providing on the upper surface of each of the lines a covering layer extending from an end part of the line and partially covering the upper surface of the line,
and the step of subjecting the lines to a metal electroplating process in which a plating potential is applied to each line at the end part whereby a metal layer is plated on the exposed surface area of the line, the covering layer serving to shield the underlying surface of the line during the plating.
With this method, the plating of the transparent conducting material results in much improved electroconductivity of the lines. Importantly, and as a consequence of using the covering layer, the metal plating obtained tends to be smoother and more uniform in thickness along the length of the line compared with the kind of metal plating layer obtained when electroplating lines whose upper surface is completely exposed. This improvement is brought about by the effect of the covering layer in the plating process and results from an understanding of the nature of the electrical currents occurring during the plating and the consequences of such to the plating layer characteristics. The transparent conducting line is basically resistive and when disposed in a plating bath with the one end held at the cathode plating potential with respect to an anode potential of the bath can be considered equivalent to a series of distributed resistances by virtue of which the current flowing through the portion closest to that end tends to be greatest. As the metal deposition rate is proportional to the current flow then plating will be faster at this portion. This in turn results in the portion being made more conductive which accelerates plating, and hence exacerbates the non-uniformity of plating. Consequently, the thickness of the plated layer obtained along the line will be significantly greater towards that end than at regions away from that end. The provision of the covering layer means that, although conduction is still through the whole width of the line at the end region, now only a partial area of the surface is subjected to plating while larger areas are involved away from that end. This means that the resistance of regions away from the end will tend to reduce, leading to enhanced plating. Although there will still be non-uniformity of the plating along the length of the line, the extent of this is considerably diminished.
The covering layer could comprise simply a strip of substantially constant width extending part way along the length of the line. Preferably, however, for better results the layer is shaped such that the uncovered area of the surface of the transparent conducting material of the line increases progressively away from the said end part along the line. The covering layer may be, for example, tapered. Alternatively, the shape of the layer may be such that its width decreases in steps along the line.
Preferably, the plating potential is applied also at an opposite end part of the line and the covering layer is arranged to extend along the line from this opposite end as well in similar manner, thus forming for example a symmetrical covering layer pattern.
The covering layer preferably comprises photoresist material.
Following the electroplating process, the covering insulating layer may be removed from the lines, and thereafter a further electroplating process may be carried out if desired.
The lines of transparent conducting material can conveniently be formed by depositing a layer of transparent conducting material over the substrate,
depositing a photoresist layer over the layer of transparent conducting material and patterning the photoresist into a configuration corresponding to the desired lines,
and patterning the transparent conducting layer using the photoresist to leave lines of transparent conducting material.
The covering insulating layers could then be provided separately by depositing a suitable layer but this would require a further patterning step to define this layer to the required shape.
In a particularly preferred embodiment, the photoresist layer used for defining the lines of transparent conducting material is used also to provide the covering layer over the lines. To this end, the layer of photoresist may be patterned into portions corresponding to the required lines with each portion including a selected region having a first thickness and corresponding in shape to that required for the covering layer, with the remainder of the portion being of reduced thickness. The defined portions of the photoresist layer are used to pattern the underlying layer of transparent conducting material, through an etching process, to leave the required lines. Thereafter, the portions of photoresist remaining on the lines are partially etched so as to remove a thickness corresponding to that of the reduced thickness areas. This results in photoresist being left at the aforementioned selected regions to constitute the covering layers and the rest of the surface of the line being exposed and ready for the electroplating operation to be performed. The patterning of the photoresist layer to achieve the desired different thickness pattern can be accomplished using a photolithographic patterning process of the kind described by C. W. Kim et al in the paper entitled xe2x80x9cA Novel Four Maskxe2x80x94Count Process Architecture for TFTxe2x80x94LCDsxe2x80x9d, published in SID 00 Digest, pages 1006-1009. The technique described, which is directed to defining TFT channels, uses so-called slit, or grey-tone, photolithography which entails exposing the (positive) photoresist through a photolithographic mask that consists of solid (opaque) areas, transparent areas, and areas with grid or slit patterns. The solid and transparent areas serve to define regions intended to be left (at full thickness) and removed respectively while the areas comprising slit patterns result in partial exposure which upon development of the photoresist leads to the areas concerned being left but with a reduced thickness.
By utilising the photoresist material to form the covering insulating layer in this manner, the number of mask steps required is kept low.
The metallic, plated, layer preferably comprises copper or silver and the transparent conducting layer preferably comprises a conductive oxide, such as ITO (Indium Tin Oxide).
The method of increasing the conductivity of transparent conducting lines is particularly useful in the manufacture of pixellated devices such as liquid crystal displays (both active matrix and passive type), LED displays, PDP (Plasma Display Panel) displays and image sensors, in which the lines are used for addressing purposes. In such devices, transparent pixel electrodes associated with the lines can conveniently be formed from the same transparent conducting layer used for the lines and defined using the same photoresist layer by suitable patterning of that photoresist layer. Preferably, photoresist material remains on the pixel electrodes during the electroplating operation in order to shield the pixel electrodes. In the preferred embodiment described above in which the photoresist is patterned to different thicknesses, then full thickness photoresist may be defined over the pixel electrodes so that photoresist still remains over the electrodes following the partial etch step.
According to a second aspect of the invention, there is provided a method of forming an active plate for a pixellated device, comprising:
depositing and patterning a gate conductor layer over an insulating substrate;
depositing a gate insulator layer over the patterned gate conductor layer;
depositing a silicon layer over the gate insulator layer;
depositing a transparent conductor layer over the silicon layer;
depositing and patterning a photoresist layer over the transparent conductor layer having a configuration defining source and drain areas, pixel electrode areas and conductor line areas associated with the source or drain conductors;
patterning the transparent conductor layer using the photoresist to form source and drains, pixel electrodes and conductor lines;
defining the photoresist to leave a photoresist region on each conductor line extending from one end part of the line partially covering the surface of the line;
and selectively electroplating the exposed areas of the transparent conductor lines with a metallic layer with a plating potential being applied at the end part of each line.
The photoresist layer is preferably patterned into areas of different thickness at the conductor lines and the step of defining the photoresist comprises partially etching the photoresist to remove the thinner areas. This method can enable a two mask process to be used, wherein the gate conductor is deposited and patterned with a first lithographic process and the photoresist layer is deposited and patterned with a second lithographic process, the silicon layer being self aligned to the gate conductor.